1. Field of the Invention
This invention relates generally to changing the clock frequency in a data processing system, and in particular to deterministically changing the clock frequency in a data processing system to achieve lower power consumption while maintaining fast interrupt handling.
2. Background of the Invention
Data processing systems (e.g., Internet appliances, consumer electronics, computers, telecommunication systems, control systems, and so forth) typically operate a processor (e.g., a micro-controller, microprocessor, central processing unit, and so forth) at a fixed clock frequency. However, a higher clock frequency leads to higher power consumption. The peak performance required by the application determines the clock frequency of the processor. The performance has two components: (1) the frequency required so that the necessary instructions can be executed within the time allowed, and (2) the frequency required so the latency/response time limit is met after an event happens. The peak performance required thus determines the overall power consumption. The interrupt response time (due to the processor clock frequency and the code that it executes for the interrupt) is typically the determining factor for the peak performance. Even if a time-sensitive interrupt occurs occasionally, the processor must run at full speed (maximum power consumption) all the time to respond to the interrupt at any time.
However, low power consumption modes have been long desired. Many conventional data processing systems are implemented with an additional state for low power consumption. Low power consumption states are typically achieved by selectively turning off entire subsystems inside the processor or in the remaining data processing system. More specifically, low power consumption in present data processing systems is typically achieved by stopping the clock to the processor in the data processing system.
However, such a low power consumption state in most conventional systems imposes a considerable time delay for the processor to regain full speed data processing system functionality, which causes longer interrupt response times than would be the case if the processor clock were always present. Other conventional systems (e.g., the ATmega 103(L) micro-controller made by Atmel Corporation, with corporate headquarters in San Jose, Calif.) either run the processor clock at full speed or turn it off completely, without the ability to selectively increase or decrease the clock frequency.
FIG. 1 is a circuit diagram of a clock structure 100, which illustrates two conventional methods to provide a low power consumption state. Clock structure 100 is comprised of a multiplexer (MUX) 116, and a glitch-free AND gate 128. The MUX 116 receives clock source 1102 and clock source 2104. MUX 116, based on a select signal 108, chooses either clock source 1102 or clock source 2104 to produce a system clock 118. System clock 118 is optionally tapped to provide clock signals 110 and 112 for one or more peripheral devices (e.g., timers and analog-to-digital converters). Glitch-free AND gate 128 receives enable signal 130 as an input signal, and produces core clock 132.
As discussed above, FIG. 1 illustrates two conventional methods. A first method selectively switches off the core clock 132 by using AND gate 128, with the advantage of low or zero overhead wakeup, and the disadvantage of providing one clock or no clock. A second method selectively switches between clock sources 102 and 104 by using MUX 116, with the advantage of choosing a clock source, and the disadvantage of taking a non-deterministic amount of time to switch between clock sources (i.e., the time to change to a new clock frequency depends on the cycle time of the old clock frequency). Present day data processing systems (e.g., using the clock generation circuit shown in FIG. 1) have a major problem with providing both low power consumption and quick handling of interrupts. Therefore, an alternative to stopping the clock to the processor and other subsystems in a data processing system is needed, that does not degrade the interrupt response time.
One fixed clock frequency for the processor, or for the data processing system, has another disadvantage. Present day data processing systems do not have the capability to increase or decrease the clock frequency according to the accessing time needed to access faster or slower memory (e.g., flash memory, or other types of non-volatile memory). For example, the processor typically services processes external to the processor (e.g., memory and I/O operations operating at slower clock frequencies), by executing processor instructions containing wait states (i.e., idle cycles) to provide enough delay time for the processor to correctly access slower memory.
Although higher clock frequencies do not facilitate these slower processes, a processor operating at higher clock frequencies is still desirable for interrupt handling. Furthermore, a change in the clock frequency over a period of many clock cycles, and/or with uncertainty in the clock transition, is also undesirable, since the data processing system can fail to operate correctly due to incorrectly-timed instruction execution. A clock change should be quick and deterministic (i.e., not depend on the old clock frequency).
What is needed is an improved implementation of clock generation in a data processing system to dynamically and deterministically increase or decrease the clock frequency as needed. Moreover, such an implementation should provide a relatively inexpensive data processing system (not significantly more expensive than a conventional data processing system) that appropriately changes the processor clock frequency for optimum performance in different circumstances (e.g., a low power mode, an interrupt mode, fast memory access mode, slow memory access mode, and other situations).
The present invention provides an improved implementation of clock generation in a data processing system to dynamically and deterministically increase or decrease the clock frequency as needed (e.g., to achieve low power consumption while maintaining fast interrupt response handling, or while accessing fast or slow memory).
The invention also provides a relatively inexpensive system that appropriately changes the processor clock frequency for optimum performance in different circumstances. The invention can be implemented in numerous ways, such as a method, a clock divider circuit, and a data processing system. Several aspects of the invention are described below.
In accordance with a first aspect of the invention, the invention provides a method to deterministically change a clock frequency between a first clock frequency and a second clock frequency in a data processing system to process operations upon the occurrence of a condition. The method includes configuring the first clock frequency to be used when processing operations in the data processing system when the condition is occurring; configuring the second clock frequency to be used when processing operations in the data processing system when the condition has not occurred; and changing the clock frequency to the first clock frequency to process the condition when the condition occurs.
In accordance with a second aspect of the invention, the invention provides a method to change the clock frequency of a data processing system to process operations upon the occurrence of a condition. The method includes configuring a first clock frequency to the clock frequency to process the condition in the data processing system when the condition is occurring; configuring a second clock frequency to the clock frequency to process operations in the data processing system when the condition has not occurred; changing the clock frequency to the first clock frequency to process the condition when the condition occurs; jumping to a condition service routine; executing the condition service routine at the first clock frequency; and testing for completion of the condition service routine.
In accordance with a third aspect of the invention, the invention provides a clock divider circuit to produce a core clock signal. The clock divider circuit includes a decoder, receiving a core clock divider value and producing a first and second output signal; a register receiving the first output signal from the decoder and producing an output signal; a control circuit receiving a plurality of inputs signals and producing an output signal; a counter receiving the output signal from the control circuit and producing an output signal; a comparator receiving the output from the register and the output signal from the counter and producing an output signal; a combinational logic circuit receiving the second output signal from the decoder and the output signal from the comparator; a clock doubling circuit receiving a clock input signal and producing a clock output signal; and a sequential logic circuit receiving the output signal from the combinational logic circuit and the output signal from the clock doubling circuit and producing the core clock signal
In accordance with a fourth aspect of the invention, the invention provides a data processing system with a deterministically variable processor clock. The data processing system includes a processor receiving said deterministically variable processor clock; a memory accessible to the processor, containing information to be used by the processor, having a first portion with a relatively faster access and a second portion with a relatively slower access; and a clock structure to change the variable processor clock supplied to the processor from a first clock frequency to a second clock frequency.